1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a virtual ground-type memory cell array.
2. Description of the Background Art
In an EEPROM (Electrically Erasable Programmable Read-Only Memory) one side of a memory transistor is, in general, connected to a source line coupled to the ground potential and it is necessary to provide source lines at predetermined intervals between bit lines and, therefore, an increase in integration density is difficult. Therefore, research concerning virtual ground-type memory cell arrays has been carried out in recent years. A virtual ground-type memory cell array (virtual ground array) is disclosed in Japanese Patent Laying-Open No. 9-82921.
In addition, NROM (Nitride Read Only Memory)-type flash EEPROMs (hereinafter referred to as NROM), which are one type of flash EEPROM from among non-volatile semiconductor memory devices, have been obtaining attention. An NROM has an ONO (Oxide Nitride Oxide) film as a gate insulating film so that two bits of information can be stored in one memory cell. Reduction in chip area per bit can be expected in an NROM, in comparison with other non-volatile semiconductor memory devices having floating gates. An NROM is disclosed in U.S. Pat. No. 6,081,456. A virtual ground-type memory cell array is used in the NROM therein.
FIG. 57 is a circuit diagram for describing how a potential is supplied to a bit line in a virtual ground-type memory cell array of a conventional NROM.
With reference to FIG. 57, a memory cell array 502 includes bit lines BL1 to BL5, word lines WL1 to WLn, memory cells 511 to 514, of which the respective gates are connected to word line WL1, and memory cells 521 to 524, of which the respective gates are connected to word line WLn.
In memory cell array 502, memory cells adjacent to each other, from among memory cells aligned in a line sharing one word line, share one bit line. That is to say, memory cell 511 and memory cell 512 are connected to bit line BL2 at a node NB so as to share bit line BL2. Memory cell 512 and memory cell 513 are connected to bit line BL3 at a node NA so as to share bit line BL3. Memory cell array 502 is a so-called virtual ground-type memory cell array wherein the bit line that corresponds to the memory cell to be accessed is connected to the ground potential.
A switching circuit 504 is provided in order to selectively supply a desired potential to a bit line of memory cell array 502. Switching circuit 504 includes switching parts 531 to 535 provided corresponding to bit lines BL1 to BL5, respectively.
Switching part 531 includes an N-channel MOS transistor 542, of which the gate receives a control signal VG1, connected between a reading power supply line 524, to which a reading power supply potential VddR is supplied via a sense amplifier circuit 501, and bit line BL1, and an N-channel MOS transistor 544, of which the gate receives a control signal GG1, connected between a ground power supply line 522, to which power potential GND is supplied, and bit line BL1.
Switching part 532 includes an N-channel MOS transistor 552, of which the gate receives a control signal VG2, connected between reading power supply line 524 and bit line BL2, and an N-channel MOS transistor 554, of which the gate receives a control signal GG2, connected between ground power supply line 522 and bit line BL2.
Switching part 533 includes an N-channel MOS transistor 562, of which the gate receives a control signal VG3, connected between reading power supply line 524 and bit line BL3, and an N-channel MOS transistor 564, of which the gate receives a control signal GG3, connected between ground power supply line 522 and bit line BL3.
Switching part 534 includes an N-channel MOS transistor 572, of which the gate receives a control signal VG4, connected between reading power supply line 524 and bit line BL4, and an N-channel MOS transistor 574, of which the gate receives a control signal GG4, connected between ground power supply line 522 and bit line BL4.
Switching part 535 includes an N-channel MOS transistor 582, of which the gate receives a control signal VG5, connected between reading power supply line 524 and bit line BL5, and an N-channel MOS transistor 584, of which the gate receives a control signal GG5, connected between ground power supply line 522 and bit line BL5.
Reading of data from the memory cell array is carried out by a current detection-type sense amplifier 501.
FIG. 58 is a cross sectional view for describing a cross sectional structure of memory cell 512 in FIG. 57.
With reference to FIG. 58, n-type impurity regions 202 and 204 are formed in a P-type substrate 200. These n-type impurity regions 202 and 204, respectively, correspond to bit lines BL2 and BL3 of FIG. 57. Bit lines BL2 and BL3 are buried-type bit lines and have a high resistance.
Silicon oxide films 206 and 208 for element isolation, respectively, are formed above n-type impurity regions 202 and 204. A silicon oxide film 210 is formed on top of a region between n-type impurity region 202 and n-type impurity region 204, and, in addition, a nitride film 212 for storing a charge is formed on top of silicon oxide film 210 and, furthermore, a silicon oxide film 214 is formed on top of nitride film 212. Such a three-layer gate insulating film is referred to as an ONO (Oxide Nitride Oxide) layered structure.
A conductive layer 216, formed of polycrystalline silicon or the like, is formed over silicon oxide films 206, 214 and 208. Conductive layer 216 corresponds to word line WL1 of FIG. 57.
Here, other memory cells of FIG. 57 have the same structure as memory cell 512 and, therefore, descriptions thereof will not be repeated.
As shown in the cross sectional view of FIG. 58, a memory cell is formed of one field effect transistor. One bit of information can be stored in a region L1 in the left side of nitride film 212 and another one bit can be stored in a region L2 in the right side of nitride film 212.
Next, programming and reading of data to and from a memory cell will be described. In the memory cell array shown in FIG. 57, each of two bit lines between which memory cells are placed is connectable to either ground power supply line 522 or reading power supply line 524. In such a configuration, the direction of voltage applied to the memory cells can freely be changed. Each memory cell has two memory regions so that programming and reading of data can be carried out to and from different memory regions by changing the direction in which current flows. In the following description, memory cell 512 is focused on as a representative memory cell.
FIG. 59 is a diagram for describing the programming operation of data to memory region L1 of memory cell 512.
With reference to FIG. 59, in the case that data written in to memory region L1, the potential of bit line BL2 is set at programming potential VddW and the potential of bit line BL3 is set at power potential GND. When word line WL1 is activated to the H level for the programming condition, a programming current Iw1 flows from bit line BL2 through non-volatile memory cell 512 toward bit line BL3. At this time, data is written in to memory region L1.
FIG. 60 is a diagram for describing the reading operation of data from memory region L1 of memory cell 512.
With reference to FIG. 60, in the case that data is reading from memory region L1, a reading power supply potential VddR is supplied to bit line BL3 via current detection-type sense amplifier circuit 501. In addition, bit line BL2 is coupled to ground potential GND. In the case wherein the potential of the bit line is set in such a manner, the threshold voltage value of the memory cell becomes greater when data is written into memory region L1.
When the setting of the potential of the bit line is completed, word line WL1 is activated to the H level for the reading condition. In the case that the threshold voltage value of the memory cell is no greater than the H level for the reading condition, a reading current Ir1 flows from bit line BL3 toward bit line BL2. The current value at this time is detected by sense amplifier circuit 501, thereby whether or not data has been programmed into memory region L1 can be read out as information.
As shown above, the direction of the current flowing at the time of the programming operation and the direction of the current flowing at the time of the reading operation become opposite to each other with respect to memory region L1.
FIG. 61 is a diagram for describing a programming operation to memory region L2 of memory cell 512.
With reference to FIG. 61, in the case that data is written into memory region L2, a programming potential VddW is supplied to bit line BL3 and bit line BL2 is coupled to the ground potential. When word line WL1 is activated to the H level for the programming condition, a programming current Iw2 flows from bit line BL3 toward bit line BL2. At this time, data is written into memory region L2.
FIG. 62 is a diagram for describing a reading operation from memory region L2 of memory cell 512.
With reference to FIG. 62, in the case that data is read out from memory region L2, reading power supply potential VddR is supplied via sense amplifier circuit 501 to bit line BL2. On the other hand, bit line BL3 is coupled to power potential GND.
In the case that the potential of the bit line is set in such a manner, the threshold voltage value of the memory cell becomes great when data is written into memory region L2. In the case that the threshold voltage value of the memory cell is small when word line WL1 is activated to the H level for the reading condition, a reading current Ir2 flows from bit line BL2 toward bit line BL3. At this time, the current is detected by sense amplifier circuit 501, thereby whether or not data has been written into memory region L2 can be sensed.
As shown above, the direction of current flow at the time of the programming operation and the direction of current flow at the time of the reading operation become opposite to each other with respect to memory region L2.
As shown in FIG. 58, bit lines 2 of the NROM are formed of diffusion layers buried beneath oxide films 206 and 208. Therefore, the bit lines have a high electrical resistance. As a result, there is a possibility wherein the performance of the NROM may be inferior to a conventional flash EEPROM.
The bit lines may be formed of metal in order to reduce the electrical resistance of the bit lines. In this case, however, the pitch of the metal wires becomes of the same pitch as of the transistors formed according to the critical dimension and there is a risk wherein defects are frequently caused by short circuiting of bit lines adjacent to each other. Accordingly, some measures will hereinafter be required to further enhance the degree of integration of non-volatile semiconductor memory devices.
An object of the present invention is to provide a non-volatile semiconductor memory device having an increased access speed while maintaining the production yield.
In summary, a non-volatile semiconductor memory device according to the present invention includes a memory cell array. The memory cell array includes: a memory cell group wherein each memory cell has first and second connection nodes and the second connection node of a memory cell is connected to the first connection node of an adjacent memory cell, except for the memory cell on each end, so that the memory cells are connected in series; and a first bit line group and second bit line connected to a plurality of first connection nodes of the memory cell group. The second bit line is formed from a wiring layer different from that for the first bit line group. The non-volatile semiconductor memory device further includes a bit line selection circuit for making a selection, as the selected bit lines, from among the first bit line group and the second bit line. The bit line selection circuit supplies a first potential to a first subgroup from among the selected bit lines and supplies a second potential different from the first potential to a second subgroup from among the selected bit lines.
Accordingly, a main advantage of the present invention is as follows: since the bit lines are formed by division into two different wiring layers, the pitch of the bit lines in one wiring layer can be widened so that an increase in integration can be obtained while maintaining the yield.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.